1. Field of the Invention
The invention relates to a method for manufacturing a planarized metal layer for a semiconductor device, and more particularly, to a method for manufacturing a planarized metal layer by depositing a first metal layer and then a second metal layer on the first metal layer such that the coverage of the step difference resulting from the formation of a contact hole is improved.
As the semiconductor device becomes more integrated, the area of the contact region provided for a certain purpose of the device decreases, so that the related aspect ratio increases. When the area of the contact region decreases and the aspect ratio increases, even coverage of the step difference decreases, thereby deteriorating the quality of the resulting device.
2. Information Disclosure Statement
Generally, in the prior art process of depositing a metal layer on a wafer, the temperature, power and pressure of the chamber are the important factors which effect the step coverage of the resulting metal layer. One method of improving the step coverage of the metal layer is to adjust the power and the pressure of the chamber. However, there is a limit to the extent of improvement in the step coverage according to the prior art process. Another method of improving the step coverage of the metal layer is by adjusting the temperature. However, a problem occurs if the temperature is undesirably high. Here the metal layer deposited on the contact hole or the via hole is diffused, resulting in a disconnected metal layer. Also, if the temperature is undesirably low, the aspect ratio of the step coverage is below 10%. Furthermore, since the metal layer is formed by utilizing a single sputtering chamber, planarization of the resulting metal layer cannot be obtained.
Therefore, it is an object of the present invention to solve the problems set forth in the prior art.
It is a further object of the present invention to provide an economical method to manufacture a level metal layer in a semiconductor device.
It is a further object of the present invention to provide a method for manufacturing a planarized metal layer for a semiconductor device by utilizing a pair of chambers with each chamber having a different temperature.
It is a further object of the present invention to provide a method for manufacturing a planarized metal layer for a semiconductor device wherein the final metal layer is a combined layer consisting of a first metal layer and a second metal layer deposited under different conditions.
It is a further object of the present invention to provide a method for manufacturing a metal layer having the predetermined thickness of the prior art metal layer, but which is a planarized metal layer consisting of a first metal layer and a second metal layer.
The preceding objects should be construed as merely presenting a few of the more pertinent features and applications of the invention. Many other beneficial results can be obtained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention may be had by referring to both the summary of the invention and the detailed description, below, which describe the preferred embodiment in addition to the scope of the invention defined by the claims considered in conjunction with the accompanying drawings.